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| Integrated Circuit Systems, Inc. ICS9160-03 Preliminary Product Preview Frequency Generator and Integrated Buffer for PowerPC(R) General Description The ICS9160-03 generates all clocks required for high speed RISC microprocessor systems based on the PowerPC 603 and 604. Five different frequency multiplying factors are selectable and offer smooth frequency transitions. BCLK signals are synchronous to PCLK and operate at PCLK/2 for optimum synchronous PCI bus performance. The multiplying and ratio factors can be customed for specific applications. Both individual and group glitch-free stop and start ofthe clock signals are provided, as well as a power-down mode to mize power consumption. The individual stop and start is provided through a serial interface control. A global output enable pin simplifies production board testing, and a test mode is available to aid in system design and diagnostics. Features * * * * * * * * * Generates four processor and seven synchronous bus clocks plus graphic, floppy, keyboard and reference clocks Selectable 33.3/50/60/66.6/80 MHz PCLKs 150ps maximum PowerPC PLL in-band jitter All synchronous clocks skew matched to 250ps Individual or group stop-clock control Power-down modes minimize standby current Custom configurations available 3.0V - 5.5 supply range 32-pin SOIC package Pin Configuration Block Diagram 28-Pin SOIC 9160-03 RevC 06/19/97P PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. ICS9160-03 Preliminary Product Preview Pin Descriptions PIN NUMBER 2 3 1 4 5, 6, 7 8, 9, 11, 12 10, 17 13 PIN NAME X1 X2 VDDX GNDX FS(0:2) PCLK(0:3) VDDP GNDP TYPE IN OUT PWR IN OUT PWR DESCRIPTION XTAL or external reference frequency input. This input includes XTAL load capacitance and feedback bias for a 10-30 MHz XTAL.** XTAL output which includes XTAL load capacitance.** XTAL oscillator circuit and REFCLK output power supplies. Frequency selection address pins. These inputs have pull-ups. Processor clock outputs which are a multiple of the input reference frequency as shown in the table below. PCLK power supplies. VDDP powers the internal PCLK PLL and the PCLK(0:3) outputs. Serial stop clock data is clocked in on the falling edge of BCLK. A total of 15 bits must be clocked in using the following protocol. SDATA is sampled on the falling edge of BCLK, so the data generator should change data on the rising edge of BCLK to ensure proper communication. SDATA must be low for one BCLK period as a start bit. The next 15 rising edges of BCLK will clock data in serially. The 16th clock enables the serial data to take effect. Outputs associated with serial data bits that are a one will continue without interruption. Clocks associated with serial data bits that are a zero will be stopped in the low state glitch-free, that is, no short clocks with the exception of REFCLK and KEYBD which do not stop. This input has an internal pull-up device. Stop clock control pins used for glitch-free start and stop of the clock outputs as described in the table on the next page. These inputs have internal pull-up devices. Buffered copy of the crystal reference frequency. Bus clock outputs having selectable frequency based on the FS(0:2) inputs (see table on next page). BCLK power supplies. VSSB and VDDB power BCLK(0:6). Fixed clock power supplies. VSSF and VDDF power GRAPHIC, FLOPPY and KEYBD outputs plus the fixed clock PLL. The floppy clock output operates at 24 MHz..* The keyboard clock output operates at 12 MHz.* The graphics system clock output operates at 40 MHz.* 14 SDATA IN 15, 16 18 19, 21, 22, 24, 25, 27, 28 20 23 26 29 30 31 32 STOP(0:1) REFCLK BCLK(0:6) GNDB VDDB GNDF VDDF FLOPPY KEYBD GRAPHIC IN OUT OUT PWR PWR OUT OUT OUT * Frequencies assuming an input or crystal of 14.318 MHz. ** Device provides 18pF load capacitance for crystal. 2 ICS9160-03 Preliminary Product Preview Functionality FS2 FS1 FS0 X1, REFCLK (MHz) PCLK (0:3) (MHKz) BCLK (0:6) (MHz) GRAPHIC (MHz) FLOPPY (MHz) KEYBD (MHz) 0* 0* 0 0 1 1 1 1 0* 0* 1 1 0 0 1 1 0* 1* 0 1 0 1 0 1 Tristate H/L* 14.318 14.318 14.318 14.318 14.318 TCLK** Tristate Off 33.3 50.0 60.0 66.6 80.0 TCLK/2 Tristate Off 16.6 25.0 30.0 33.3 40.0 TCLK/4 Tristate H/L* 40.0 40.0 40.0 40.0 40.0 TCLK/3 Off H/L* 24.0 24.0 24.0 24.0 24.0 TCLK/5 Tristate H/L* 12.0 12.0 12.0 12.0 12.0 TCLK/10 * The oscillator and all PLLs are stopped to minimize power consumption in modes `000' and `001.' All outputs maintain their last stable value in mode `001.' Control signals STOP0 and STOP1 can be used to ensure glitch-free start and stop when entering mode `001,' provided mode `001' is entered after the clocks have stopped and exited 10ms (maximum PLL lock time) prior to starting clocks. ** X1 is externally driven with TCLK in mode `111.' Group Clock Control STOP1 + STOP0 + SDATA * PCLK (0:1) PCLK (2:3) BCLK (0;6) GRAPHIC, FLOPPY KEYBD, REFCLK 0 0 1 1 0 1 0 1 1 1 1 1 Low Low Low Running Low Low Running Running Low Running Running Running Low Running Running Running Running Running Running Running Outputs stop and start glitch-free within on-clock period. Outputs will not change state if the PLLs are off. * Each output can be stopped and started glitch-free as described in the SDATA pin description above. +SDATA control and STOP(0:1) control are logically ORed for each individual clock. 3 ICS9160-03 Preliminary Product Preview Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.5 V to V DD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . 0 to +70C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics at 3.3V VDD = 3.0 - 3.7 V, TA = 0 - 70 C unless otherwise stated DC Characteristics PARAMETER Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Current Output High Current Output Low Current Output High Current Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage Supply Current SYMBOL VIL VIH IIL IIH IOL1 IOH1 IOL1 IOH1 VOL VOH1 VOL1 VOH1 ICC TEST CONDITIONS MIN 0.7VDD TYP 10.5 47.0 -66.0 38.0 -47.0 0.3 2.8 0.3 2.8 60 MAX 0.2VDD 28.0 5.0 -42.0 -30.0 0.4 0.4 130 UNITS V V mA mA mA mA mA mA V V V V mA VIN=0V VIN=VDD VOL=0.8V; for PCLKS & BCLKS VOL=2.0V; for PCLKS & BCLKS VOL=0.8V; for fixed CLKs VOL=2.0V; for fixed CLKs IOL=15mA; for PCLKS & BCLKS IOH=-30mA; for PCLKS & BCLKS IOL=12.5mA; for fixed CLKs IOH=-20mA; for fixed CLKs @66.66 MHz; all outputs unloaded -5.0 30.0 25.0 2.4 2.4 - Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production. 4 ICS9160-03 Preliminary Product Preview Electrical Characteristics at 3.3V VDD = 3.0 - 3.7 V AC Characteristics PARAMETER Rise Time Fall Time Rise Time Fall Time Duty Cycle Jitter, One Sigma Jitter, Absolute Jitter, One Sigma Jitter, Absolute Input Frequency Clock Skew Clock Skew Clock Skew SYMBOL Tr 1 TEST CONDITIONS 20pF load, 0.8 to 2.0V 20pF load, 2.0 to 0.8V 20pF load, 20% to 80% 20pF load, 80% to 20% 20pF load PCLK & BCLK Clocks; Load=20pF, FOUT>25 MHz PCLK & BCLK Clocks; Load=20pF, FOUT>25 MHz Fixed CLK and BCLK < 25 MHz and Fixed CLK; Load=20pF Fixed CLK and BCLK < 25 MHz; Load=20pF PCLK to PCLK; Load=20pF; @1.4V BCLK0 to other BCLK; Load=20pF; @1.4V PCLK to BCLK; Load=20pF; @1.4V MIN 40 -250 -3.0 -5.0 -250 -500 1 TYP 1.5 0.9 2 1.8 50 50 1 2 14.318 50 90 2.6 MAX 3 2 4.5 4.25 60 150 250 3.0 5.0 250 500 5 UNITS ns ns ns ns % ps ps % % MHz ps ps ns Tf1 Tr1 Tf1 Dt1 Tj1s1 Tjab1 Tj1s1 Tjab1 Fi1 Tsk 1 Tsk1 Tsk1 Note 1: Note 2: Parameter is guaranteed by design and characterization. Not 100% tested in production. Jitter spectrum meets PowerPC PLL natural frequency in-band requirements of less than 150ps. 5 ICS9160-03 Preliminary Product Preview The data is latched into the internal shift register on the falling edge of the BCLK signal with the BCLK as a reference (see waveform above). The SDATA input pattern will change at the BCLK rising edges and must be stable for loading into the shift register at the BCLK falling edges. Programming Bit Addresses The following table lists the function of each of the 15 input programming bits for the device. ICS9160-03 SDATA Serial Stop Clock Input Pin Bit Pattern BIT# OUTPUT PIN 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 32 n/a 30 28 27 21 22 24 25 19 n/a 12 11 9 8 STOP CLOCK FUNCTION (Clocks stops if Bit=Low) START BIT (One "zero" bit needed to start shift register sequence.) GRAPHIC FLOPPY BCLK6 BCLK5 BCLK4 BCLK3 BCLK2 BCLK1 BCLK0 PCLK3 PCLK2 PCLK1 PCLK0 6 ICS9160-03 Preliminary Product Preview 32-Pin SOIC Package LEAD COUNT DIMENSONL 32L .804 Ordering Information ICS9160M-03 Example: ICS XXXX M - PPP Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type M=SOIC Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. 7 |
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